1. Field of the Invention
The present invention relates to a display panel drive device for driving a display panel such as a plasma display panel (hereinafter referred to as a ‘PDP’) or an electroluminescence (hereinafter referred to as ‘EL’) panel, or the like.
2. Description of the Related Art
Nowadays, thin-type display devices that employ a flat self-illumination-type display panel such as a PDP or EL are being manufactured as the so-called “wall-mount” televisions. Such a technology as that described in Japanese Patent Kokai No. 2000-155557 is known as a display panel drive device of thin-type display devices employing a PDP, for example. Here, the overall constitution of the display panel drive device disclosed in this publication is shown in the block diagram of FIG. 1.
In this figure, the PDP10, which is a display panel, comprises row electrodes X1 to Xn and row electrodes Y1 to Yn, which form a row electrode pair corresponding with each row (the first to nth rows) of a single screen by means of one pair of an X electrode and Y electrode. In addition, column electrodes Z1 to Zm, which are orthogonal to the row electrode pairs and correspond with each column of a single screen (first to mth columns) with a dielectric layer and discharge gap layer (not shown) interposed therebetween, are formed in the PDP10. Further, one discharge cell C(i,j) is formed at the intersection between a pair of row electrodes (Xi, Yi) and one column electrode Zj.
Each electrode in the PDP10 is connected to a column electrode drive circuit 20 and row electrode drive circuit 30 or 40, and these electrode drive circuits are drive-controlled by means of commands from a drive control circuit 50.
The overall operation of the display panel drive device shown in FIG. 1 may be described as follows.
First, the row electrode drive circuit 30 generates a positive-voltage reset pulse RPy and simultaneously applies same to all of the row electrodes Y1 to Yn as shown in FIG. 2. At the same time, the row electrode drive circuit 40 generates a negative-voltage reset pulse RPX and simultaneously applies same to each of the row electrodes X1 to Xn.
Due to the simultaneous application of the reset pulses RPX and RPY, all of the discharge cells of the PDP10 are excited and charged particles are generated. After the discharge has ended, a predetermined amount of barrier charge is formed uniformly in the dielectric layers of all the discharge cells. Incidentally, this processing step is known as the reset step.
After the reset step is complete, the column electrode drive circuit 20 generates pixel data pulses DP1 to DPn that comply with pixel data corresponding with the first to nth rows of the screen. Subsequently, these pixel data pulses are sequentially applied to the column electrodes Z1 to Zm as shown in FIG. 2. Meanwhile, the row electrode drive circuit 30 generates a negative-voltage scan pulse SP in accordance with the application timing of each of the pixel data pulses DP1 to DPn. This negative-voltage scan pulse SP is then sequentially applied to the row electrodes Y1 to Yn with the timing shown in FIG. 2.
Among the discharge cells belonging to row electrodes to which the scan pulse SP is applied, discharge occurs in the discharge cells to which a positive-voltage pixel data pulse DP is simultaneously applied, whereby the majority of the barrier charge is lost. On the other hand, because discharge does not take place in the discharge cells to which the scan pulse SP is applied but to which the positive-voltage pixel data pulse DP is not applied, the barrier charge still remains. Here, discharge cells in which the barrier charge remains are light-emitting discharge cells and discharge cells in which the barrier charge is eliminated are non-light-emitting discharge cells. Incidentally, this processing step is known as the address step.
When the address step is complete, the row electrode drive circuit 30 applies a positive-voltage sustain pulse IPy serially to each of the row electrodes Y1 to Yn as shown in FIG. 2. At the same time, the row electrode drive circuit 40 applies the positive-voltage sustain pulse IPX serially to each of the row electrodes X1 to Xn with timing that is displaced with respect to the application timing for the sustain pulse IPY. Light-emitting discharge cells, in which the barrier charge still remains over the period during which these sustain pulses IPX and IPY are alternately applied, repeat discharge light emission and retain this light-emitting state. Incidentally, this processing step is known as the sustain step.
Further, in the case of the display panel drive device shown in FIG. 1, the serial processing step described above is repeated for each subfield of the display image.
Further, the first drive control circuit 50 of FIG. 1 generates a variety of switching signals for generating a variety of drive pulses as shown in FIG. 2, based on the synchronization timing contained in the picture signal supplied to this device. Further, these switching signals are supplied to the column electrode drive circuit 20, and row electrode drive circuits 30 and 40 respectively. That is, each of the column electrode drive circuit 20 and the row electrode drive circuits 30 and 40 generate the variety of drive pulses shown in FIG. 2 in accordance with the switching signals supplied by the drive control circuit 50.
The pulse generation circuit, which generates various drive pulses such as the reset pulse RPY and sustain pulses IPX and IPY, is provided for each of the electrodes in each row and column, in each of the electrode drive circuits described above. Further, these pulse generation circuits all generate the variety of drive pulses above by utilizing the charging of the capacitor by an LC resonance circuit constituted by an inductor L and a capacitor C.
That is, considering that a discharge cell C(i,j) formed on the PDP10 is a capacitive load, a resonance circuit is formed by combining an inductor, which is an inductive element, and a capacitor for power recovery with this discharge cell C(i,j). Further, the desired drive pulse is generated by causing this resonance circuit to oscillate with predetermined timing by opening and closing a switching element such as an FET in accordance with the switching signals supplied by the drive control circuit 50.
As described above, a conventional display panel drive device performs reset discharge processing, such as a display-screen full screen write discharge or a full screen erase discharge, in the reset step that starts a one-field or one-subfield picture display. In other words, it can be deduced that the barrier-charge state of all the discharge cells on the panel is initiated by means of this reset discharge and is included in the writing of data in the subsequent address step.
However, at the time of a transition, such as when the power supply of the display panel drive device is disconnected, cases arise where the voltage value supplied to the circuit of each part in the device drops and control of the variety of discharge states described above is problematic. For example, a situation may also arise where, when the device's power supply is disconnected in the course of a subfield sequence and hence the drive sequence is interrupted, the device is then left with a lot of charge still remaining in the discharge cells on the panel. In this case, there is the risk that, when the power supply of the device is turned on next, the large amount of electrical charge remaining in the discharge cells will flow into each of the electrode drive circuits and render the operation of each electrode drive circuit unstable.